Self-timed circuitry is useful for very large scale integration ("VLSI") circuits. Self-timed circuitry outputs one or more signals in response to an asynchronous signal. The asynchronous signal is representative, for example, of a next instruction or request.
During a waiting period, the self-timed circuitry waits for the asynchronous signal. During the waiting period, the self-timed circuitry consumes less power because it performs fewer operations. Moreover, self-timed circuitry achieves faster cycle times because its asynchronous operation is not constrained by a predetermined worst-case clock frequency.
By comparison, traditional synchronous circuitry operates in response to a synchronous clock signal, which is constrained by a predetermined worst-case clock frequency. Relative to comparable self-timed circuitry, the synchronous circuitry consumes extra power. This is because clock signals continue transitioning within the synchronous circuitry, even while the synchronous circuitry is not performing an operation. This extra power can be significant. For example, it is possible for clock circuitry to consume 30% of a synchronous VLSI circuit's total power.
Nevertheless, self-timed circuitry does present challenges. For example, self-timed integrated circuitry is relatively difficult to test. By comparison, synchronous integrated circuitry is more readily testable according to Level Sensitive Scan Design ("LSSD") techniques.
LSSD techniques are less practically applied to self-timed integrated circuitry, because self-timed integrated circuitry is asynchronous and therefore includes fewer latches. Moreover, the boundary between state elements and combinational logic is less clear within self-timed circuitry, due to its asynchronous mutual handshaking protocol. Accordingly, LSSD compatible latches are more difficult to implement within self-timed integrated circuitry.
Instead, self-timed integrated circuitry is more readily tested by applying stimuli to the circuitry's inputs and monitoring the circuitry's outputs. By applying stimuli, testing of self-timed integrated circuitry is more difficult within large dataflow systems. Also, it is more difficult to reduce the frequency of self-timed circuitry in order to match slower test hardware.
Thus, a need has arisen for a method and circuitry for testing self-timed circuitry, in which self-timed integrated circuitry is more practically testable.